The ASIC division of Texas Instruments Deutschland had to implement a complex SoC for Network Access Infrastructure, which adopted a 0.13 µm technology with 7 metal layers. The system complexity was 6 Mio. gates and had parts running at frequencies of 450 MHz. Physical timing closure of one of the sub-chips of this design was difficult to achieve, because of its U-shape and the complex requisites of its clock distribution. A. Uber took over the physical implementation of such sub-chip, whose complexity was 2.2 Mio. Gates not including memory blocks [...], and had parts running at frequencies of 300 MHz.
[...] he actually exceeded our expectations: he immediately understood the critical nodes of our design flow and leveraged his design experience to fully solve our challenges.
